Optimal performance in a power-optimized package

The Origin™ E2 is designed for power-starved applications such as mobile phones and edge nodes. By eliminating the need for external DRAM access, the E2 deep learning accelerator (DLA) saves system power while increasing performance, reducing latency, and cutting system BOM costs. Its highly efficient engine uses less than 1W for 18 TOPS performance. Origin E2 is tunable for specific workloads to provide an optimal performance profile for unique application requirements.

  • Performance efficient 18 TOPS/Watt
  • Scalable performance from 2-9K INT8 MACS
  • Capable of processing real-time HD video and images on-chip
  • Advanced activation memory management
  • Low latency
  • Tunable for specific workloads
  • Hardware scheduler for NN
  • Support for standard NN functions including Convolution, Deconvolution, FC, Activations, Reshape, Concat, Elementwise, Pooling, Softmax, Bilinear
  • Processes model as trained, no need for software optimizations
  • Use familiar open-source platforms like TFlite
  • Delivered as soft IP: portable to any process

Advantages

Industry-leading performance and power efficiency.

Industry-leading performance and power efficiency (up to 18 TOPS/W)

Drastically reduces memory requirements.

Architected to serve wide range of compute requirements.

No DRAM required.

Drastically reduces memory requirements, no off-chip DRAM required.

Drastically reduces memory requirements.

Run trained models unchanged without the need for hardware dependent optimizations.

Run trained models unchanged without the need for hardware dependent optimizations.

Deterministic, real-time performance.

Improved performance for your workloads, while still running breadth of models.

Improved performance for your workloads, while still running breadth of models.

Simple software stack.

Simple software stack.

Achieve same accuracy your trained model.

Achieve same accuracy your trained model.

Simplifies deployment to end customers.

Simplifies deployment to end customers.

Benefits

  • Efficiency: industry-leading 18 TOPS/W enables greater processing efficiencies with lower power consumption
  • Simplicity: eliminates complicated compilers, easing design complexity, reducing cost, and speeding time-to-market
  • Configurability: independently configurable building blocks allow for design optimization– right sized deployments
  • Predictability: deterministic, QoS
  • Scalability: from 1 to 20 TOPS a single scalable architecture addresses a wide range of application performance requirements
  • Deployability: best-in-market TOPS/mm2 assures ideal processing/chip size designs
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